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hi-8282a pin configuration (top view) general description the hi-8282a is a silicon gate cmos device for interfacing the arinc 429 serial data bus to a 16-bit parallel data bus. two receivers and an independent transmitter are provided. the receiver input circuitry and logic are designed to meet the arinc 429 specifications for loading, level detection, timing, and protocol. the transmitter section provides the arinc 429 communication protocol. additional interface circuitry such as the holt hi-8585, hi-8586 or hi-3182 is required to translate the 5 volt logic outputs to arinc 429 drive levels. the 16-bit parallel data bus exchanges the 32-bit arinc data word in two steps when either loading the transmitter or interrogating the receivers. the data bus interfaces with cmos and ttl. timing of all the circuitry begins with the master clock input, clk. for arinc 429 applications, the master clock frequency is 1 mhz. each independent receiver monitors the data stream with a sampling rate 10 times the data rate. the sampling rate is software selectable at either 1mhz or 125khz. the results of a parity check are available as the 32nd arinc bit. the hi-8282a examines the null and data timings and will reject erroneous patterns. for example, with a 125 khz clock selection, the data frequency must be between 10.4 khz and 15.6 khz. the transmitter has a first in, first out (fifo) memory to store 8 arinc words for transmission. the data rate of the transmitter is software selectable by dividing the master clock, clk, by either 10 or 80. the master clock is used to set the timing of the arinc transmission within the required resolution. applications ? avionics data communication ? serial to parallel conversion ? parallel to serial conversion features ? arinc specification 429 compliant ? 16-bit parallel data bus ? direct receiver interface to arinc bus ? timing control 10 times the data rate ? selectable data clocks ? 8 word transmit fifo ? ? self test mode ? parity functions ? low power, single 5 volt supply ? industrial & extended temperature ranges ? alternate source to intersil hs-3282 in all arinc 429 applications ? small footprint 44-pin qfp package option ? automatic transmitter data timing receiver error rejection per arinc specification 429 44-pin plastic quad flat pack (pqfp) (see page 10 for additional package pin configurations) 44 - n/c 43 - 429di2(b) 42 - 429di2(a) 41 - 429di1(b) 40 - 429di1(a) 39 - vcc 38 - n/c 37 - 36 - txclk 35 - clk 34 - n/c mr 33 - n/c 32 - n/c 31 - 30 - entx 29 - 28 - 429do 27 - tx/r 26 - 25 - 24 - bd00 23 - bd01 cwstrx 429do pl2 pl1 n/c-12 bd10 - 13 bd09 - 14 bd08 - 15 bd07 - 16 bd06 - 17 gnd-18 bd05 - 19 bd04 - 20 bd03 - 21 bd02 - 22 n/c - 1 -2 -3 sel - 4 -5 -6 bd15 - 7 bd14 - 8 bd13 - 9 bd12 - 10 bd11 - 11 d/r1 d/r2 en1 en2 hi-8282apqi hi-8282apqt hi-8282apqm (ds8282a rev. h) 07/13 arinc 429 serial transmitter and dual receiver july 2013 holt integrated circuits www.holtic.com (
pin description hi-8282a symbol function description vcc power +5v 5% 429di1 (a) input arinc receiver 1 positive input 429di1 (b) input arinc receiver 1 negative input 429di2 (a) input arinc receiver 2 positive input 429di2 (b) input arinc receiver 2 negative input output receiver 1 data ready flag output receiver 2 data ready flag sel input receiver data byte selection (0 = byte 1) (1 = byte 2) input data bus control, enables receiver 1 data to outputs input data bus control, enables receiver 2 data to outputs if is high bd15 i/o data bus bd14 i/o data bus bd13 i/o data bus bd12 i/o data bus bd11 i/o data bus bd10 i/o data bus bd09 i/o data bus bd08 i/o data bus bd07 i/o data bus bd06 i/o data bus gnd power 0 v bd05 i/o data bus bd04 i/o data bus bd03 i/o data bus bd02 i/o data bus bd01 i/o data bus bd00 i/o data bus input latch enable for byte 1 entered from data bus to transmitter fifo. input latch enable for byte 2 entered from data bus to transmitter fifo. must follow . tx/r output transmitter ready flag. goes low when arinc word loaded into fifo. goes high after transmission and fifo empty. 429do output "ones" data output from transmitter. output "zeroes" data output from transmitter. entx input enable transmission input clock for control word register clk input master clock input tx clk output transmitter clock equal to master clock (clk), divided by either 10 or 80. input master reset, active low d/r1 d/r2 en1 en2 en1 pl1 pl2 pl1 429do cwstr mr holt integrated circuits 2
functional description data bus function control description pin if enabled, an internal connection bdo5 self test 0 = enable is made passing 429do and to the receiver logic inputs receiver 1 if enabled, arinc bits 9 and, bdo6 decoder 1 = enable 10 must match the next two control word bits if receiver 1 decoder is bdo7 - - enabled, the arinc bit 9 must match this bit if receiver 1 decoder is bdo8 - - enabled, the arinc bit 10 must match this bit receiver 2 if enabled, arinc bits 9 and bdo9 decoder 1 = enable 10 must match the next two control word bits if receiver 2 decoder is bd10 - - enabled, then arinc bit 9 must match this bit if receiver 2 decoder is bd11 - - enabled, then arinc bit 10 must match this bit invert logic 0 enables normal odd parity bd12 xmtr 1 = enable and logic 1 enables even parity parity output in transmitter 32nd bit bd13 xmtr data 0 = 10 clk is divided either by 10 or clk select 1 = 80 80 to obtain xmtr data clock bd14 rcvr dta 0 = 10 clk is divided either by 10 or clk select 1 = 80 80 to obtain rcvr data clock 429do control word register the hi-8282a contains 10 data flip flops whose d inputs are con- nected to the data bus and clocks connected to . each flip flop provides options to the user as follows: cwstr the receivers arinc bus interface figure 1 shows the input circuit for each receiver. the arinc 429 specification requires the following detection levels: the hi-8282a guarantees recognition of these levels with a common mode voltage with respect to gnd less than 5v for the worst case condition (4.75v supply and 13v signal level). design tolerances guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. if the arinc signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data. state differential voltage one +6.5 volts to +13 volts null +2.5 volts to -2.5 volts zero -6.5 volts to -13 volts hi-8282a-10 the hi-8282a-10 option is similar to the hi-8282a with the exception that it allows an external 10k to 15k ohm resistor to be added in series with each arinc input without affecting the arinc input thresholds. this option is especially useful in applications where lightning protection circuitry is also required. each side of the arinc bus must be connected through a 10k to 15k ohm series resistor in order for the chip to detect the correct arinc levels. the typical 10 volt differential signal is translated and input to a window comparator and latch. the comparator levels are set so that with the external 10k to 15k ohm resistors, they are just below the standard 6.5 v minimum arinc data threshold and just above the 2.5 v maximum arinc null threshold. the receivers of the hi-8282a-10, when used with external 15k ohm resistors, will withstand do-160f, level 3, waveforms 3, 4, 5a and 5b pin injection. no additional lightning protection circuit is necessary. please refer to the holt an-300 application note for additional information and recommendations on lightning protection of holt line drivers and receivers. v cc gnd gnd 429di1(b) or 429di2(b) 429di1(a) or 429di2(a) differential amplifiers ones comparators null zeroes v cc figure 1. arinc receiver input arinc 429 data format the following table shows the bit positions in exchanging data with the receiver or transmitter. arinc bit 1 is the first bit transmitted or received. data bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bus 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 arinc 13 12 11 10 9 31 30 32 12345678 bit byte 1 byte 2 data bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bus 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 arinc 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 bit hi-8282a holt integrated circuits 3
functional description (cont.) sel en d/r decoder control bits / mux control latch enable control 32 to 16 driver 32 bit latch 32 bit shift register to pins control bit bd14 clock option clock clk bit counter and end of sequence parity check 32nd bit data bit clock eos word gap word gap timer bit clock end start sequence control error clock error detection shift register shift register null zeros shift register ones eos bits9&10 figure 2. receiver block diagram hi-8282a receiver logic operation bit timing bit rate pulse rise time pulse fall time pulse width figure 2 is a block diagram showing each receiver?s logic. arinc 429 specifies the following timing for received data: 100k bps 1% 12k -14.5k bps 1.5 0.5 sec 10 5 sec 1.5 0.5 sec 10 5 sec 5 sec 5% 34.5 - 41.7 sec the hi-8282a accepts signals meeting these specifications and re- jects signals outside these tolerances using the method described here: 1. the timing logic requires an accurate 1.0 mhz clock source. less than 0.1% error is recommended. 2. the sampling shift registers are 10 bits long and must show three consecutive ones, zeros or nulls to be consid- ered valid data. to qualify data bits, one or zero in the upper bits of the sampling shift register must be followed by null in the lower bits within the data bit time. a word gap null re- quires three consecutive nulls in both the upper and lower bits of the sampling shift register. this guarantees the mini- mum pulse width. high speed low speed 3. each data bit must follow its predecessor by not less than 8 samples and not more than 12 samples. in this manner the bit rate is checked. with exactly 1 mhz input clock frequency, the acceptable data bit rates are as follows: 83k bps 10.4k bps 125k bps 15.6k bps data bit rate min data bit rate max high speed low speed 4. the word gap timer samples the null shift register every 10 input clocks (80 for low speed) after the last data bit of a valid reception. if the null is present, the word gap counter is incremented. a count of 3 enables the next reception. the 32nd bit of received arinc words stored in the receive fifo is used as a parity flag indicating whether good odd parity is re- ceived from the incoming arinc word. the parity bit is reset to indicate correct parity was received and the resulting word is then written to the receive fifo. the receiver sets the 32nd bit to a ?1?, indicating a parity error and the resulting word is then written to the receive fifo. therefore, the 32nd bit retrieved from the receiver fifo will al- ways be a ?0? when valid (odd parity) arinc 429 words are re- ceived. once 32 valid bits are recognized, the receiver logic generates an end of sequence (eos). if the receiver decoder is enabled and the 9th and 10th arinc bits match the control word program bits or if the receiver decoder is disabled, then eos clocks the data ready flag flip flop to a "1", or (or both) will go low. the data flag for a receiver remains low until after arinc bytes from that receiver are retrieved. this is accomplished by first acti- vating with sel, the byte selector, low to retrieve the first byte and then activating with sel high to retrieve the second byte. retrieves data from receiver 1 and retrieves data from re- ceiver 2. if another arinc word is received and a new eos occurs before the two bytes are retrieved, the data is overwritten by the new word. receiver parity odd parity received even parity received retrieving data d/r1 d/r2 en en en1 en2 both holt integrated circuits 4
functional description (cont.) transmitter a block diagram of the transmitter section is shown in figure 3. the fifo is loaded sequentially by first pulsing to load byte 1 and then to load byte 2. the control logic automatically loads the 31 bit word in the next available position of the fifo. if tx/r, the transmitter ready flag, is high (fifo empty), then 8 words, each 31 bits long, may be loaded. if tx/r is low, then only the available positions may be loaded. if all 8 positions are full, the fifo ignores further attempts to load data. when entx goes high, enabling transmission, the fifo positions are incremented with the top register loading into the data transmission shift register. within 2.5 data clocks the first data bit appears at either 429do or . the 31 bits in the data transmission shift register are presented sequentially to the outputs in the arinc 429 format with the following timing: arinc data bit time 10 clocks 80 clocks data bit time 5 clocks 40 clocks null bit time 5 clocks 40 clocks word gap time 40 clocks 320 clocks the word counter detects when all loaded positions are trans- mitted and sets the transmitter ready flag, tx/r, high. fifo operation data transmission pl1 pl2 429do high speed low speed transmitter parity the parity generator counts the ones in the 31-bit word. if the bd12 control word bit is set low, the 32nd bit transmitted will make parity odd. if the control bit is high, the parity is even. the two receivers are independent of the transmitter. therefore, control of data exchanges is strictly at the option of the user. the only restrictions are: 1. the received data may be overwritten if not retrieved within one arinc word cycle. 2. the fifo can store 8 words maximum and ignores attempts to load addition data if full. 3. byte 1 of the transmitter data must be loaded first. 4. either byte of the received data may be retrieved first. both bytes must be retrieved to clear the data ready flag. 5. after entx, transmission enable, goes high it cannot go low until tx/r, transmitter ready flag, goes high. otherwise, one arinc word is lost during transmission. self test system operation if the bd05 control word bit is set low, 429do or are internally connected to the receivers inputs, bypassing the interface circuitry. data to receiver 1 is as transmitted and data to recevier 2 is the complement. 429do and outputs remain active during self test. 429do 429do master reset ( ) mr upon master reset, data transmission and reception are immediately terminated, the transmit fifo and receivers cleared as are the transmit and receive flags. the control word register is not affected by a master reset. figure 3. transmitter block diagram bit bd12 data clock control bit bd13 pl1 pl2 clk tx clk parity generator data and null timer sequencer bit and word gap counter start sequence word counter and fifo control increment word count data clock divider fifo loading sequencer 429do 429do 8 x 31 fifo 31 bit parallel load shift register bit clock word clock address load data bus tx/r entx hi-8282a holt integrated circuits 5
functional description (cont.) data rate - example pattern 429do 429do arinc bit null data data data null null word gap bit 1 next word bit 32 bit 31 bit 30 loading control word cwhld t cwset t cwstr t data bus cwstr valid receiver operaton data ready flag d/r arinc data byte select sel enable byte on bus en data bus bit 31 bit 32 selen t d/r t ensel t dataen t d/ren t end/r t en t ensel t selen t dataen t endata t endata t enen t don't care don't care don't care byte 1 valid byte 2 valid timing diagrams hi-8282a repeater operation repeater mode of operation allows a data word received by the hi-8282 to be placed directly into the transmit fifo for transmission. after a 32-bit word has been shifted into the receiver shift register, the flag goes low. a logic "0" is placed on the sel line and is strobed. this is the same procedure as for normal receiver operation, placing the lower byte (16) of the data word on the data bus. by strobing at the same time as d/r en pl1 en, the byte is also transferred into the transmit fifo. sel is then taken high and is strobed again to place the upper data word byte onto the data bus. by strobing at the same time as , the second data word byte is also transferred to the transmit fifo. the data word is now ready for transmission, according to the parity programmed into the control word register. in normal (non-repeater) operation, either byte of the received data word may be read first by using the sel input. during repeater operation however, data word lower byte must always be read first. while the data is being read, it is loading concurrently into the transmit fifo, which always loads lower byte first. en pl2 en holt integrated circuits 6
timing diagrams (cont.) transmitter operation pl2 dwset t dwhld t tx/r t dwhld t pl12 t pl t data bus pl1 tx/r byte 2 valid pl t pl12 t dwset t byte 1 valid transmitting data arinc bit 429do or 429do pl2 entx tx/r pl2en t endat t dtx/r t entx/r t data bit 1 data bit 2 data bit 32 repeater operation timing don't care 429di d/r en pl1 pl2 sel tx/r entx 429do bit 32 don't care d/r t en t d/ren t enen t en t end/r t selen t ensel t enpl t plen t selen t ensel t enpl t plen t tx/r t tx/ren t endat t entx/r t dtx/r t null t bit 1 bit 32 hi-8282a holt integrated circuits 7
vcc = 5v 5%, gnd = 0v, ta = operating temperature range (unless otherwise specified). min typ max operating supply current: i 20 ma cc2 standby supply current: i 20 ma cc1 supply input - v cc output capacitance: c 15 pf o (all other outputs) output source i v = v - 0.4v 1.1 ma oh out cc output current: output sink i v = 0.4v 2.6 ma ol out (bi-directional pins) output source i v = v - 0.4v 1.1 ma oh out cc output current: output sink i v = 0.4v 3.0 ma ol out logic "0" output voltage v i = 2.6ma 0.4 v ol ol output voltage: logic "1" output voltage v i = -1.5ma 2.7 v oh oh outputs - , , bd00 through bd15, tx/r, 429do, & tx clk d/r1 d/r2 429do input source i -20 a il input current: input sink i 10 a ih input voltage lo v 0.7 v il input voltage: input voltage hi v 3.5 v ih all other inputs - sel, , , , , entx, en1 en2 pl1 pl2 cwstr mr , clk & input source i -1.5 a il input current: input sink i 1.5 a ih input voltage lo v 0.7 v il input voltage: input voltage hi v 2.1 v ih bi-directional inputs - bd00 through bd15 to vcc c 20 pf h (guaranteed but not tested) to gnd c 20 pf g input capacitance: differential c pins 2 to 3, 4 to 5 20 pf i input source i -450 a il input current: input sink i 200 a ih to vcc r 12 27 k h to gnd r 12 27 k g input resistance: differential r 12 k i null v with respect to gnd -2.5 0 2.5 v nul zero v mode voltage less than 5v -13.0 -10.0 -6.5 v il differential input voltage: one v arinc input pins: common 6.5 10.0 13.0 v ih arinc inputs - 429di1 (a), 429di1 (b), 429di2 (a) & 429di2 (b) parameter conditions unit symbol limits supply voltage vcc -0.3v to +7v voltage at arinc inputs -120v to +120v voltage at any other pin -0.3v to vcc +0.3v dc current drain per input pin 10ma power dissipation 500mw operating temperature range: (industrial) -40c to +85c (extended) -55c to +125c storage temperature range: -65c to +150c note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings dc electrical characteristics absolute maximum ratings hi-8282a holt integrated circuits 8
ac electrical characteristics vcc = 5v, gnd = 0v, ta = operating temperature range and fclk = 1mhz 0.1% with 60/40 duty cycle + limits parameter symbol units min typ max control word timing receiver timing fifo timing transmission timing pulse width - t 130 ns setup - data bus valid to high t 130 ns hold - high to data bus hi-z t 0 ns delay - start arinc 32nd bit to low: high speed t 16 s low speed t 128 s delay - low to l0w t 0 ns delay - low to high t 200 ns setup - sel to l0w t 20 ns hold - sel to high t 20 ns delay - l0w to data bus valid t 200 ns delay - high to data bus hi-z t 30 ns pulse width - or t 200 ns spacing - high to next l0w t 50 ns pulse width - or t 200 ns setup - data bus valid to high t 110 ns hold - high to data bus hi-z t 10 ns spacing - or t 0 ns delay - high to tx/r low t 840 ns spacing - high to entx high t 0 s delay - 32nd arinc bit to tx/r high t 400 ns spacing - tx/r high to entx l0w t 0 ns cwstr cwstr cwstr d/r d/r en en d/r en en en en en1 en2 en en pl1 pl2 pl pl pl1 pl2 pl2 pl2 cwstr cwset cwhld d/r d/r d/ren end/r selen ensel endata dataen en enen pl dwset dwhld pl12 tx/r pl2en dtx/r entx/r delay - entx high to txa(out) or txb(out): high speed t 25 s delay - entx high to txa(out) or txb(out): low speed t 200 s delay - low to low t 0 ns hold - high to high t 0 ns delay - tx/r low to entx high t 0 ns t 200 ns 1% endat endat enpl plen tx/ren mr repeater operation timing master reset pulse width arinc data rate and bit timing en pl pl en hi-8282a holt integrated circuits 9
additional hi-8282a pin configurations (see page 1 for the 44-pin plastic quad flat pack ) hi-8282apji hi-8282apjt hi-8282apjm hi-8282acji hi-8282acjt hi-8282acjm 44-pin j-lead cerquad 44-pin ceramic lcc nc () tx clk (xmit clock out) clk (master clk in) nc nc () entx (enable xmit) () 429do (xmit data) tx/r (xmit ready flag) () () bd00 bd01 bd02 bd03 bd04 bd05 gnd mr master reset cwstr control word strobe 429do xmit data pl2 xmit byte 2 le pl1 xmit byte 1 le 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vcc (rec. 1 input) 429di1(a) (rec.1 input) 429di1(b) (rec. 2 input) 429di2(a) (rec. 2 input) 429di2(b) () () (rec. byte select) sel () () bd15 bd14 bd13 bd12 bd11 bd10 bd09 bd08 bd07 bd06 rec.1 data flag d/r1 rec.2 data flag d/r2 rec. 1 output enable en1 rec. 2 output enable en2 hi-8282acli hi-8282clt hi-8282clm 40-pin ceramic side brazed dip 44-pin plastic plcc hi-8282acdi / cdt / cdm hi-8282a holt integrated circuits 10
ordering information notes: 1. the -10 configuration requires an external 10k to 15k ohm resistor in series with each arinc input to guarantee specified voltage thresholds. the 15k ohm resistors are required to withstand do-160f, level 3, waveforms 3 ,4,5a&5bpin injection. hi - 8282a (ceramic) cx x -xx hi - 8282a (plastic) px x x -xx 44 pin plastic j-lead plcc (44j) package description part number pj pq 44 pin plastic quad flat pack (44ptqs) temperature range flow burn in -40c to +85c no i -55c to +125c -55c to +125c no yes t m part number t m i part number f blank lead finish tin / lead (sn / pb) solder 100% matte tin (pb-free, rohs compliant) input series resistance built-in required externally part number 25 kohm -10 (note 1) 0 no dash number 35 kohm 10k to 15k ohm package description 40 pin ceramic side brazed dip (40c) part number cd cl cj 44 pin ceramic leadless chip carrier (44s) 44 pin j-lead cerquad (44u) temperature range flow burn in -40c to +85c no i -55c to +125c -55c to +125c no yes t m part number t m i lead finish tin / lead (sn / pb) solder gold gold input series resistance built-in required externally part number 25 kohm -10 (note 1) 0 no dash number 35 kohm 10k to 15k ohm hi-8282a holt integrated circuits 11
revision history revision date description of change ds8282a, rev. g 02/01/09 clarified the ?t? temperature range. clarified series resistance values for ?-10? devices. rev. h 07/30/13 updated bit timing, receiver parity and qfp package information. changed ?hi-temp? operating conditions to ?extended?. update voltage at arinc input pins from +/-29v to +/-120v. hi-8282a holt integrated circuits 12
hi-8282a package dimensions inches (millimeters) package type: 40c 40-pin ceramic side-brazed dip bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .085 .009 (2.159 .229) .610 .010 (15.494 .254) .600 .010 (15.240 .254) .595 .010 (15.113 .254) .010 .002 .001 (.254 .051 .025) .100 (2.54) bsc 2.020 (51.308) .225 (5.715) max .125 (3.175) min max .050 (1.270) typ .018 (.457) typ 44-pin j-lead cerquad inches (millimeters) package type: 44u bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) 2 1 44 43 .620 .012 (15.748 .305) .688 .005 (17.475 .127) .650 .010 (16.510 .254) sq. .200 (5.080) max .050 (1.270) .019 .002 (.483 .051) .100 .007 (2.540 .178) bsc .039 .005 (.990 .127) sq. max holt integrated circuits 13
hi-8282a package dimensions 44-pin plastic plcc inches (millimeters) package type: 44j bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) pin no. 1 ident .045 x 45 .045 x 45 pin no. 1 .173 .008 (4.394 .203) .690 .005 (17.526 .127) sq. .610 .020 (15.494 .508) .031 .005 (.787 .127) .653 .004 (16.586 .102) sq. .017 .004 (.432 .102) .050 (1.27) bsc detail a r .010 .001 (.254 .03) .020 (.508) min see detail a .035 .010 (.889 .254) package type: 0 7 detail a see detail a sq. 44pmqs 44-pin plastic quad flat pack (pqfp) .009 (.23) .520 .010 (13.20 .25) .394 .004 (10.0 .10) sq. max. .014 .003 (.37 .08) .035 .006 (.88 .15) .005 (.13) r min. .012 (.30) r max. .079 .008 (2.0 .20) .096 (2.45) max. .0315 (.80) inches (millimeters) bsc bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) holt integrated circuits 14
hi-8282a package dimensions bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) 44-pin ceramic leadless chip carrier inches (millimeters) package type: 44s .651 .011 (16.535 .279) sq. .075 .004 (1.905 .101) .326 .006 (8.280 .152) pin 1 .050 (1.270) .009r .006 (.229r .152) .092 028 (2.336 .711) .025 .003 (.635 .076) .050 005 (1.270 .127) pin 1 bsc .020 (.508) index .040 x 45 (1.016 x 45) 3 plcs holt integrated circuits 15

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